Semiconductor device

ABSTRACT

A semiconductor device which materializes dynamic threshold operation, on the assumption of the application of a bulk semiconductor substrate. The semiconductor substrate has a first conductivity type well region ( 11 ), a source region ( 12 ) and a drain region ( 13 ) of second conductivity type are made in the vicinity of the surface of the first conductivity type of well region ( 11 ), a channel region ( 14 ) is provided between these regions ( 12  and  13 ), a gate insulating film ( 15 ) and a gate electrode ( 16 ) are stacked in order on the channel region ( 14 ), and the gate electrode ( 16 ) is connected to the well region ( 11 ) through the contact hole (not shown in the figure) of the gate insulating film ( 15 ). In this transistor, as compared with a conventional SOI substrate, the resistance of the well region ( 11 ) can be lowered to about one-tenth.

This application is a 35 U.S.C. §371 filing of International PatentApplication No. PCT/JP97/04344, filed Nov. 27, 1997. This applicationclaims priority benefit of Japanese Patent Application No. 8-324465,filed Dec. 4, 1996.

TECHNICAL FIELD

The present invention relates to a semiconductor device in the form of atransistor which operates at a low power supply voltage by dynamicallychanging a threshold, and a semiconductor device incorporating such atransistor. The present invention also relates to a device separationtechnique suitable for integration of such semiconductor devices.

BACKGROUND ART

In a CMOS circuit (a complementary circuit), the power consumption isproportional to the square of the power supply voltage. Therefore, it iseffective to reduce the power supply voltage for reducing the powerconsumption of a CMOS LSI. However, as the power supply voltage isreduced, the driving power of the transistor decreases, thereby posing aproblem of an increase in the delay time of the circuit. This problembecomes more significant the more the power supply voltage is reduced.Particularly, it has been known that the increase becomes significantwhen the power supply voltage is three times the threshold or less.

A possible way to improve this is to reduce the threshold. However, asthe threshold is reduced, the leak current when the gate is OFFincreases, the lower limit of the threshold is defined by the acceptableOFF current.

In order to alleviate such a problem, there has been proposed, as atransistor for a low power supply voltage, a dynamic threshold operationtransistor which realizes a high driving power at a low voltage byreducing an effective threshold when a transistor is ON (A DynamicThreshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation, F.Assaderaghi et al., IEDM94 Ext. Abst. p.809).

FIG. 19 illustrates a simplified structure of such a dynamic thresholdoperation transistor (hereinafter, referred to as a “DTMOS”). While aNMOS is illustrated, a PMOS can also be realized with symmetricallyopposite polarities.

As illustrated in the figure, an SOI substrate 1 is used, and a gate 3and the substrate 1 are locally short-circuited with an oversized metalline 2. The essential element is the short-circuiting of the gate 3 andthe substrate 1 with each other, and the way they are short-circuited isnot limited to the one illustrated.

When a gate bias is applied in the structure in which the gate and thesubstrate are short-circuited, a forward bias of the same magnitude asthe gate bias is applied to a substrate active region. Thus, the samebiased state as that in an ordinary translstor results when the gate isOFF. When the gate is ON, the substrate is forwardly biased as the gatebias increases. As a result, the threshold decreases.

However, in this structure, it is necessary, for suppressing thestand-by current, to limit the voltage applied to the gate to about 0.6V, a voltage at which a lateral parasitic bipolar transistor ts turnedON.

When the gate bias (=body bias) is OPP, such a DTMOS has a leak currentcomparable to that of an ordinary transistor provided on an SOIsubstrate and having the same channel state. While the DTMOS is ON, asthe gate bias (=body bias) increases, the threshold further decreases,whereby the gate overdrive effect increases, thereby significantlyincreasing the driving power. The fact that deterioration of mobility issuppressed by the suppression of a vertical electric field on thesubstrate surface also contributes to the increase in the driving power.Moreover, since the lateral parasitic bipolar transistor is OFF, thesignificant increase in the stand-by current is suppressed.

However, since the above-described conventional DTMOS uses an SOIsubstrate, the thickness of the body (the depth of the channel region)is very small (50 nm-200 nm), thereby resulting in a very highresistance. Thus, even if the gate and the body are short-circuited witheach other via a contact, a potential is less likely to be transferredto the body at a position farther away from the contact, and the CR timeconstant increases. Therefore, in view of a transient operation, theeffect as a DTMOS is suppressed, and it cannot be operated at a highspeed.

Thus, the present invention has been made to solve such problems in theprior art, and has an objective of providing a semiconductor devicewhich realizes a dynamic threshold operation assuming the application ofa bulk semiconductor substrate in order to solve the increase in thebody resistance of the SOI substrate.

DISCLOSURE OF THE INVENTION

Before the present invention is illustrated, a structure of asemiconductor device based on which the present invention has been madewill be discussed.

A semiconductor device based on which the present invention has beenmade comprises: a semiconductor substrate; a well region of a firstconductivity provided on the semiconductor substrate; a source regionand a drain region of a second conductivity provided on the well regionof the first conductivity type; a channel region provided between thesource region and the drain region; a gate insulation film provided onthe channel region; and a gate electrode provided on the gate insulationfilm, wherein the gate electrode is electrically connected to the wellregion corresponding to the gate electrode.

In such a structure, the resistance of the well region corresponds tothe body resistance of the above-described conventional Sol substrate,and the resistance of the well region can be made very small.

More particularly, the body of the above-described conventional SOIsubstrate has a width equal to the gate length and a length equal to thegate width. Moreover, as described above, the thickness is very thin,i.e., 50 nm-200 nm, and the resistance thereof is very high. Forexample, when the concentration of the body (i.e., the channelconcentration which cannot be high due to the need to reduce thethreshold of the transistor) is 1×10¹⁷/cm³, and the thickness of thebody is 100 nm, the sheet resistance is then about 10 KΩ. When the gatelength is 0-2 μm, and the gate width is 10 μm, the aspect ratio is then50, and the resistance value is 500 KΩ, which is 50 times as great asthe sheet resistance.

On the contrary, in the semi conductor device based on which the presentinvention has been made, the depth of the well region can be set freely.

For example, the width of the well region needs to be at least equal tothe total width occupied by the source region, the drain region, and thegate region. In view of the fact that a contact region is providedbetween the source region and the drain region, it is reasonable to setthe width of each of the source region and the drain region to be threetimes as great as the gate length. Thus, the minimum width of the wellregion needs to be equal to the sum of the width of the source region,the width of the drain region, and the length of the gate region. Thus,it is reasonable to set the minimum width to be seven times as great asthe length of the gate region.

Assuming that the length of the well region is equal to the width of thegate region, the aspect ratio is 1/7.

Moreover, even when the concentration of the well region is the same asthat of the body of the SOI substrate, the well region is not limited inthe depth direction. Therefore, when the depth is set to 1 μm to bewithin a reasonable range, the sheet resistance of the well region is1/10 of that of the body of the SOI substrate.

In view of the aspect ratio and the sheet resistance, the resistance ofthe well region can be reduced to about 1/70 of that of the body of theSOI substrate.

Next, a semiconductor device of the present invention which solves theabove-described problems based on the semiconductor device having such astructure will be described.

A semiconductor device of claim 1 comprises: a semiconductor substrate;a deep well region of a first conductivity type provided in thesemiconductor substrate: a shallow well region of a second conductivitytype provided in the deep well region; a source region and a drainregion of the first conductivity type provided in the shallow wellregion; a channel region provided between the source region and thedrain region; a gate insulation film provided on the channel region; anda gate electrode provided on the gate insulation film, wherein: the gateelectrode is electrically connected to the shallow well regioncorresponding to the gate electrode; the shallow well region iselectrically separated from an adjacent shallow well region on thesemiconductor surface; and a high impurity concentration region issandwiched between low impurity concentration regions.

With such a structure in which the high impurity concentration region issandwiched between the low impurity concentration regions, theresistance of the well region can be further reduced. With such astructure, it is possible to effectively reduce the resistance of thewell region by the high concentration region in the middle of theshallow well region, while maintaining a low threshold by one of the lowconcentration regions on the channel side, without increasing parasiticcapacitances of the source region and the drain region (when theimpurity concentration of the shallow well region at the junctionbetween the source region and the drain region is high, the depletionlayer does not sufficiently extend, thereby increasing the junctioncapacitance). and without increasing the parasitic capacitance betweenone of the low concentration regions in the shallow well region existingon the deeper well region side and the deep well region.

The sheet resistance can be reduced to some tens of ohms, though thereduction depends upon the concentration of the high concentrationregion in the middle. In this case, the shallow well region has a sheetresistance of about 1/100-1/1000 of the body resistance of theconventional Sot substrate, so that, assuming that the aspect ratio is1/7, the resistance can be reduced to about 1/700-1/7000 of the bodyresistance of the conventional SOI substrate.

Moreover, in this case, the shallow well region is electricallyseparated from the shallow well region on the semiconductor surface.This structure is necessary when a circuit configuration of a pluralityof elements is assumed, since a fundamental structural feature of thepresent invention is the connection between the gate electrode and theshallow well region.

In the semiconductor device of claim 1, it is preferred that theadjacent shallow well regions are electrically separated from each otherby a groove-shaped separation structure which is deeper than the shallowwell region but shallower than the deep well region, as set forth inclaim 2. With this structure, the area in the bulk semiconductorsubstrate to be occupied by one transistor can be made comparable tothat of a DTMOS provided on the SOI substrate.

A semiconductor device of claim 3 comprises: a semiconductor substrate;a deeper well region of a first conductivity type provided in thesemiconductor substrate; a deep well region of a second conductivitytype provided in the deeper well region: a shallow well region of thefirst conductivity type provided in the deep well region of the secondconductivity type; a source region and a drain region of the secondconductivity type provided on in the shallow well region; a channelregion provided between the source region and the drain region; a gateinsulation film provided on the channel region; and a gate electrodeprovided on the gate insulation film, wherein: the gate electrode iselectrically connected to the shallow well region corresponding to thegate electrode: the deep well region and the shallow well region areelectrically separated from an adjacent deep well region and an adjacentshallow well region, respectively; and the shallow well region includesa high impurity concentration region sandwiched between low impurityconcentration regions.

In such a structure, the deeper well region may be provided between theadjacent deep well regions so as to electrically separate the adjacentdeep well regions from each other. Particularly, when providing acomplementary element having p-type and n-type deep well regionstogether on a single semiconductor substrate, the deep well regions areseparated by a deeper well region having an opposite conductivity type,whereby it is possible to ground the n-type deep well region to GND, andto set the p-type deep well region to the power supply voltage.

On the contrary, in the above-described semiconductor substrate based onwhich the present invention has been made, if a complementary element isprovided with p-type and n-type deep well regions together on a singlesemiconductor substrate, the p-type and n-type deep well regions are incontact with each other, thereby forming a PN junction between the deepwell regions. With this limitation, It is necessary to set the n-typedeep well region to the power supply voltage and to ground the p-typedeep well region to GND (when the n-type deep well region is grounded toGND while fixing the p-type deep well region to the power supplyvoltage, a forward current continuously flows regardless of theoperation of the element).

In the semiconductor device of claim 3, it is preferred that the deepwell region and the shallow well region are electrically separatedrespectively from the adjacent deep well region and the adjacent shallowwell region by a groove-shaped separation structure which is deeper thanthe deep well region but shallower than the deeper well region, as setforth in claim 4. This structure has an effect that the area in the bulksemiconductor substrate to be occupied by one transistor can be madecomparable to that of a DTMOS provided on the SOI substrate.

As set forth in claim 5, when a complementary circuit is provided withthe semiconductor device of claim 1 or 3, the design of a CMOS logic ofMOSFETs as in the prior art can be used directly. Moreover, since thesemiconductor device of the present invention is one which realizes theabove-described dynamic threshold operation, it is possible to realize adevice which operates at a high speed with very low power consumption.

On the contrary, the CMOS logic formed of DTMOSs using the conventionalSOI substrate has an excessively large body resistance as describedabove, and thus cannot operate at a high speed and thus cannot follow atransient operation. Then, the effect of a DTMOS cannot be expected.

Next, a semiconductor device of claim 6 comprises: a semiconductorsubstrate of a first conductivity type; a groove-shaped separationregion formed in the semiconductor substrate; L plurality of island-likeactive regions separated from one another by the groove-shapedseparation region; a deep well region of a second conductivity typeprovided in at least one of the island-like active regions, the deepwell region of the second conductivity type being surrounded by thegroove-shaped Separation region; a shallow well region of the firstconductivity type provided for one of island-like active regions wherethe deep well region surrounded by the groove-shaped separation exists,the shallow well region of the first conductivity type being surroundedby the groove-shaped separation region; a shallow well region of thesecond conductivity type provided for another one of the island-likeactive regions where the deep well region surrounded by thegroove-shaped separation does not exist, the shallow well region of thesecond conductivity type being surrounded by the groove-shapedseparation region: a source region and a drain region of the secondconductivity type provided in the shallow well region of the firstconductivity type; a source region and a drain region of the firstconductivity type provided in the shallow well region of the secondconductivity type; channel regions provided between the source regionand the drain region of the first conductivity type and between thesource region and the drain region of the second conductivity type; agate insulation film provided on each of the channel regions; and a gateelectrode provided on the gate insulation film, wherein: each gateelectrode is electrically connected to the shallow well regioncorresponding to the gate electrode: and the shallow well region of thefirst conductivity type, the shallow well region of the secondconductivity type, and the deep well region of the second conductivitytype are electrically separated respectively from an adjacent shallowwell region of the first conductivity type, an adjacent shallow wellregion of the second conductivity type, and an adjacent deep well regionof the second conductivity type.

A semiconductor device of claim 7 comprises: a semiconductor substrate;a deeper well region of a first conductivity type provided on thesemiconductor substrate; a groove-shaped separation region provided inthe deeper well region; a plurality of island-like active regionsseparated from one another by the groove-shaped separation region; adeep well region of a second conductivity type provided in at least oneof the is land-like active regions, the deep well region of the secondconductivity type being surrounded by the groove-shaped separationregion; a shallow well region of the first conductivity type providedfor one of the island-like active regions where the deep well regionsurrounded by the groove-shaped separation region exists, the shallowwell region of the first conductivity type being surrounded by thegroove-shaped separation region: a shallow well region of the secondconductivity type provided for another one of the island-like activeregions where the deep well region surrounded by the groove-shapedseparation region does not exist, the shallow well region of the secondconductivity type being surrounded by the groove-shaped separationregion; a source region and a drain region of the second conductivitytype provided in the shallow well region of the first conductivity type;a source region and a drain region of the first conductivity typeprovided in the shallow well region of the second conductivity type;channel regions provided between the source region and the drain regionof the first conductivity type and between the source region and thedrain region of the second conductivity type; a gate insulation filmprovided on each of the channel regions; and a gate electrode providedon the gate insulation film, wherein: each gate electrode iselectrically connected to the shallow well region corresponding to thegate electrode; and the shallow well region of the first conductivitytype, the shallow well region of the second conductivity type, and thedeep well region of the second conductivity type are electricallyseparated respectively from an adjacent shallow well region of the firstconductivity type, an adjacent shallow well region of the secondconductivity type, and an adjacent deep well region of the secondconductivity type.

Moreover, a semiconductor device of claim 8 comprises: a semiconductorsubstrate of a first conductivity type: a groove-shaped separationregion provided in the semiconductor substrate; a plurality ofisland-like active regions separated from one another by thegroove-shaped separation; a deep well region of the first conductivitytype provided in at least one of the island-like active regions, thedeep well region of the first conductivity type being surrounded by thegroove-shaped separation: a deep well region of a second conductivitytype provided in another one of the island-like active regions where thedeep well region of the first conductivity type does not exist, the deepwell region of the second conductivity type being surrounded by thegroove-shaped separation region; a shallow well region of the secondconductivity type provided in an upper portion of the deep well regionof the first conductivity type, the shallow well region of the secondconductivity type being surrounded by the groove-shaped separationregion: a shallow well region of the first conductivity type provided inan upper portion of the deep well region of the second conductivitytype, the shallow well region of the first conductivity type beingsurrounded by the groove-shaped separation; a source region and a drainregion of the second conductivity type provided in the shallow wellregion of the first conductivity type; a source region and a drainregion of the first conductivity type provided in the shallow wellregion of the second conductivity type; channel regions provided betweenthe source region and the drain region of the first conductivity typeand between the source region and the drain region of the secondconductivity type; a gate insulation film provided on each of thechannel regions; and a gate electrode provided on the gate insulationfilm, wherein: each gate electrode is electrically connected to theshallow well region corresponding to the gate electrode; and the shallowwell region of the first conductivity type, the shallow well region ofthe second conductivity type, the deep well region of the firstconductivity type, and the deep well region of the second conductivitytype are electrically separated respectively from an adjacent shallowwell region of the first conductivity type, an adjacent shallow wellregion of the second conductivity type, an adjacent deep well region ofthe first conductivity type, and an adjacent deep well region of thesecond conductivity type.

The structures of claims 6, 7 and 8 are preferred for realizing acomplementary circuit, and allow for free arrangement of n-channel andp-channel elements, without increasing the area to be occupied by atransistor or having to provide a boundary rule between the well regions(the n well and the p well must be separated by at least a certaindistance so that latch-up does not occur).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view schematically illustrating a semiconductor device basedon which the present invention has been made.

FIG. 2 is a view schematically illustrating a conventional DTMOS.

FIG. 3 is a view schematically illustrating a semiconductor deviceaccording to the first embodiment of the present invention.

FIG. 4 is a graph illustrating a relationship between a gate voltage anda drain current when a potential of a shallow well region is varied in atransistor of the present invention.

FIG. 5 illustrates a semiconductor device according to the secondembodiment of the present invention, wherein: (a) is a plan viewthereof; (b) is a cross-sectional view thereof along b—b′ in (a); (c) isa cross-sectional view thereof along c-c′ in (a); and (d) it across-sectional view thereof along d-d′ in (a).

FIG. 6 is a graph illustrating a relationship between a gate voltage anda drain current in an n-channel transistor having a structure asillustrated in FIG. 5.

FIG. 7 is a graph illustrating a relationship between a gate voltage anda drain current in a p-channel transistor having a structure asillustrated in FIG. 5.

FIG. 8 illustrates a variation of the semiconductor device of FIG. 5,wherein: (a) is a plan view thereof: (b) is a cross-sectional viewthereof along b-b′ in (a); (c) is a cross-sectional view thereof alongc-c′ in (a); and (d) is across-sectional view thereof along d-d′ in (a).

FIG. 9 is a view schematically illustrating a layout of a transistor ofthe present invention and a parasitic bipolar transistor.

FIG. 10 schematically illustrates a semiconductor device according tothe third embodiment of the present invention, wherein: (a) is a planview thereof (b) is a cross-sectional view thereof along b-b′ in (a);(c) is a cross-sectional view thereof along c-c′ in (a); and (d) is across-sectional view thereof along d-d′ in (a).

FIG. 11 schematically illustrates a semiconductor device according tothe fourth embodiment of the present invention, wherein: (a) is a planview thereof; and (b) is a cross-sectional view thereof along b-b′ in(a).

FIG. 12 is a cross-sectional view illustrating a variation of thesemiconductor device of FIG. 11.

FIG. 13 is a cross-sectional view illustrating another variation of thesemiconductor device of FIG. 11.

FIG. 14 schematically illustrates a semiconductor device according tothe fifth embodiment of the present invention, wherein: (a) is a planview thereof: and (b) is a cross-sectional view thereof along b-b′ in(a).

FIG. 15 schematically illustrates a semiconductor device according tothe sixth embodiment of the present invention, wherein: (a) is a planview thereof; and (b) is a cross-sectional view thereof along b-b′ in(a).

FIG. 16 schematically illustrates a semiconductor device according tothe seventh embodiment of the present invention, wherein: (a) is a planview thereof; and (b) is a cross-sectional view thereof along b-b′ in(a).

FIG. 17 schematically illustrates a variation of the semiconductordevice of FIG. 16, wherein: (a) is a plan view thereof: and (b) is across-sectional view thereof along b-b′ in (a).

FIG. 18 illustrates a semiconductor device according to an example ofthe present invention, wherein: (a) is a cross-sectional view thereof;and (b) and (c) each are a graph illustrating an effective carrierconcentration along a-a′ in (a).

FIG. 19 is a view schematically illustrating a conventional DTMOS.

BEST MODE FOR CARRYING OUT THE INVENTION

First, in order to assist the understanding of the present invention, asimplified structure of a semiconductor device, based on which thepresent invention has been made, will be described with reference toFIG. 1.

Referring to FIG. 1, a semiconductor substrate (a bulk semiconductorsubstrate) of the semiconductor device (hereinafter, referred to also asa “transistor”) comprises: a well region 11 of a first conductivitytype; a source region 12 and a drain region 13 of a second conductivitytype provided in the vicinity of the surface of the well region 11 ofthe first conductivity type; a channel region 14 provided between theregions 12 and 13: and a gate insulation film 15 and a gate electrode 16deposited in this order on the channel region 14, wherein the gateelectrode 16 is connected to the well region 11 via a contact hole (notshown) in the gate insulation film 15.

In this case, the source region 12 and the drain region 13 requirerespectively sufficient areas for providing a contact hole for lineconnections. Therefore, the width of each of the source region 12 andthe drain region 13, is set to be three times as great as the gatelength L (a generally-employed minimum process dimension) i.e., acommonly acceptable dimension. Moreover, w denotes the gate width, d1denotes the depth of the channel region 14, d1+d2 denotes the depth ofthe well region 11, and ρ denotes the specific resistance of the wellregion 11. Furthermore, R1 denotes the resistance of the channel region14, R2 denotes the resistance of the source region 12, the drain region13, and a region below the channel region 14. Then, the resistance R ofthe well region 11 is expressed as in Expression (1) below.$\begin{matrix}{R = \quad \frac{1}{\frac{1}{R_{1}} + \frac{1}{R_{2}}}} & {\quad {{Expression}\quad (1)}} \\{= \quad {\frac{1}{\frac{1}{\frac{W}{L}\frac{\rho}{d_{1}}} + \frac{1}{\frac{W}{7L}\frac{\rho}{d_{2}}}} = \frac{W\quad \rho}{L\left( {d_{1} + {7d_{2}}} \right)}}} & {\quad {{Expression}\quad (1)}}\end{matrix}$

Where a DTMOS of the conventional SOI substrate illustrated in FIG. 19is formed as illustrated in FIG. 2, so that the dimensions andstructures of the source region, the drain region and the channel regionof the DTMOS are matched with those of the device illustrated in FIG. 1,and where the concentration of the body is made to be equal to that ofthe well region 11, and the specific resistance of the body is denotedby ρ, the body resistance R0 is then expressed as in Expression (2)below. $\begin{matrix}{R_{0} = {\frac{W}{L}\frac{\rho}{d_{1}}}} & {{Expression}\quad (2)}\end{matrix}$

As can be seen from the expression, the depth of the channel region 14and the thickness of the body are denoted commonly by d1 and are equallyset to 100 nm, for example. The depth d1+d2 of the well region 11 is setto 1 μm. Then, d1=9d2, and the resistance R of the well region 11 isexpressed as in Expression (3) below. $\begin{matrix}{R = {\frac{W\quad \rho}{L\left( {d_{1} + {63\quad d_{1}}} \right)} = {\frac{W\quad \rho}{64\quad {Ld}_{1}} = \frac{R_{0}}{64}}}} & {{Expression}\quad (3)}\end{matrix}$

Therefore, in the transistor based on which the present invention hasbeen made, it is possible to reduce the resistance R of the well region11 to {fraction (1/64)} of that of the conventional SOI substrate.

The concentration of the well region 11 and the concentration of thebody of the conventional SOI substrate were assumed to be 1×10¹⁷/cm² asan average concentration. It is noted that the latter body concentrationof the SOI substrate is directly related to, and limited by, thethreshold.

The illustrated dimensions of the well region 11, the source region 12,the drain region 13, the channel region 14, etc., are merelyillustrative, and can be changed to various other dimensions.

FIG. 3 schematically illustrates a semiconductor device according to thefirst embodiment of the present invention. In the figure, members thatprovide similar functions to those of FIG. 1 are provided with likereference numerals.

The device of the first embodiment corresponds to the device of claim 1.

In this embodiment, the well region 11 has a structure in which a highimpurity concentration region 17 is sandwiched between low impurityconcentration regions 16. This structure provides further reduction inthe resistance. Moreover, the well region 11 is electrically separatedfrom an adjacent shallow well region on the semiconductor surface.

In the conventional SOI substrate, the body concentration directlyaffects the threshold, as described above, whereby the bodyconcentration cannot be increased.

On the contrary, when using a bulk semiconductor substrate as in thisembodiment, the impurity concentrations of regions other than thechannel region in the well region can be increased so as to freely setthe resistance of the well region irrespective of the threshold. Forexample, the relationship between the impurity concentration and theresistance is discussed on page 32 of the text of “Physics ofSemiconductor Devices, 2nd Edition: written by S. M. Sze”. Theresistance can be dramatically changed depending upon the impurityconcentration. A concentration difference between a concentration on theorder of 10¹⁷ and a concentration on the order of 10¹⁹ per cubiccentimeter results in a resistance difference of about 1.5-2 orders ofmagnitude (of course, a higher concentration results in a lowerresistance).

For example, when the region 17 having a high impurity concentration of1×10¹⁹/cm² is provided in the well region 11 of 1×10¹⁷/cm² in the firstembodiment, a further reduction in resistance from that of FIG. 1 by anorder of magnitude or more can be provided. The high impurityconcentration region 17 is buried at a position away from the channelregion 14, and thus does not affect the threshold.

Now, the basic operation of the transistor of the present invention willbe analyzed.

First, the following simplified Expression (4) shows the relationshipbetween the threshold V_(th) of an ordinary MOSFET and the bias(V_(s-well)) of the shallow well region. $\begin{matrix}{V_{th} = {{2\varphi_{b}} + \frac{2{qN}_{s - {well}}{ɛ_{s}\left( {{2\varphi_{b}} - V_{s - {well}}} \right)}}{C_{OX}} + V_{FB}}} & {{Expression}\quad (4)}\end{matrix}$

Herein, Φb denotes the Fermi potential, N_(s-well) denotes an impurityconcentration of the shallow well region, ε_(s) denotes the dielectricconstant of the shallow well region, q denotes a quantity of the chargeof an electron, C_(ox) denotes a gate insulation film capacitance perunit area, and V_(FB) denotes a flat band voltage.

It can be seen from Expression (4) above that the absolute value of thethreshold decreases when the shallow well region is forwardly biased.

The simplified expression of the driving current is expressed as inExpression (5) below in a linear domain. $\begin{matrix}{I_{D} = {\frac{W}{L}\mu_{eff}{C_{OX}\left\lbrack {{\left( {V_{GS} - V_{th}} \right)V_{DS}} - {\frac{1}{2}V_{DS}^{2}}} \right\rbrack}}} & {{Expression}\quad (5)}\end{matrix}$

It is expressed as in Expression (6) below in a saturation domain.$\begin{matrix}{I_{D} = {\frac{1}{2}\frac{W}{L}\mu_{eff}{C_{OX}\left( {V_{GS} - V_{th}} \right)}^{2}}} & {{Expression}\quad (6)}\end{matrix}$

Herein, I_(D) denotes the drain current, a denotes the gate width, Ldenotes the gate length, μ_(eff) denotes the effective mobility, V_(GS)denotes the gate potential with respect to the source potential, anddenotes V_(DS) the drain potential with respect to the source potential.

The graph of FIG. 4 illustrates the relaltionship between the gatevoltage and the drain current when the potential of the shallow wellregion is varied. Herein, the gate voltage refers to a gate electrodepotential with respect to a source region potential.

With the driving current expressed as in Expressions (5) and (6), it ispossible to obtain a larger driving current at a dramatically smallerpower supply voltage as the absolute value of the threshold V_(th)decreases.

In the translator of the present invention, the gate electrode and theshallow well region are connected together, whereby the potential of theshallow well region changes as the gate potential changes. Therefore, asis apparent from the expressions above, the shallow well region isforwardly biased, and thus the apparent threshold V_(th)′ decreases asthe gate potential changes (for n-channel transistors, a positivepotential with respect to the source potential is applied to the gateelectrode; for p-channel transistors, a negative potential with respectto the source potential is applied to the gate electrode). As a result,it is possible to obtain a large driving current by a low power supplyvoltage. This effect is particularly significant when the power supplyvoltage is small.

Therefore, the threshold V_(th)″ of the transistor of the presentinvention can be obtained as a solution to the simultaneous equations ofExpressions (4) and (7) below. $\begin{matrix}{V_{th} = {{2\varphi_{b}} + \frac{2{qN}_{s - {well}}{ɛ_{s}\left( {{2\varphi_{b}} - V_{s - {well}}} \right)}}{C_{OX}} + V_{FB}}} & {{Expression}\quad (4)}\end{matrix}$

V _(th) =V _(GS) =V _(s-well)  Expression (7)

Expression (6) above expresses a drain current in a saturation domain(the speed of a circuit is determined by this amount of current and theCR time constant), and V_(th) in Expression (6) is the value when thepotential V_(s-well) of the well region is at the power supply voltage.In an ordinary MOSEET, the well region and the source region are at thesame potential, and thus the threshold stays constant even when the gatevoltage changes. In the transistor of the present invention, on theother hand, the gate electrode and the shallow well region areshort-circuited with each other, and thus the potential V_(s-well) ofthe well region changes according to the gate potential, therebychanging the apparent threshold. Then, Expression (6) can be rearrangedinto Expression (8) below assuming that the power supply voltage isV_(DD) and V_(th) for V_(GS)=V_(s-well)=V_(DD) is the apparent V_(th)′.$\begin{matrix}{I_{D} = {\frac{1}{2}\frac{W}{L}\mu_{eff}{C_{OX}\left( {V_{G} - V_{th}^{\prime}} \right)}^{2}}} & {{Expression}\quad (8)}\end{matrix}$

In short, there is a relationship as follows among the threshold V_(th)of an ordinary MOSFET when the source region and the well region of theMOSFET are at the same potential, the threshold V_(th)″ of thetransistor of the present invention, and the apparent threshold V_(th)′of the transistor of the present invention.

V _(th)′(V _(GS) =V _(s-well) =V _(DD))<V _(th)″(V _(GS) =V _(s-well) =V_(th)″)<V _(th)(V _(sub) =V _(s): typically set to the ground potential)

Herein, V_(sub) denotes the potential of the substrate (the well), andV_(s) denotes the source potential.

In the transistor of the present invention, the apparent thresholdV_(th)′ can be dramatically reduced from the threshold V_(th) of theordinary MOSFET.

For the transistor of the present invention, Expression (9) below can beobtained by replacing the current and the voltage in Expression (8) withthe driving current (I_(drive)) and the power supply voltage (VDD).$\begin{matrix}{I_{drive} = {\frac{1}{2}\frac{W}{L}\mu_{eff}{C_{OX}\left( {V_{DD} - V_{th}^{\prime}} \right)}^{2}}} & {{Expression}\quad (9)}\end{matrix}$

For the ordinary MOSFET, Expression (10) below can be obtained byreplacing the current and the voltage in Expression (6) with the drivingcurrent (I_(drive)) and the power supply voltage (V_(DD)).$\begin{matrix}{I_{drive} = {\frac{1}{2}\frac{W}{L}\mu_{eff}{C_{OX}\left( {V_{DD} - V_{th}} \right)}^{2}}} & {{Expression}\quad (10)}\end{matrix}$

In an ordinary MOSFET, the threshold cannot be reduced sufficiently dueto an influence of the short channel effect. On the contrary, thetransistor of the present invention is very advantageous for a low powersupply voltage (when V_(DD) is small). For example, when V_(DD)=0.6 Vand V_(th)=0.3 V, V_(th)′ is about 0.15 V, and (V_(DD)−V_(th))² and(V_(DD)−V_(th)′)² are 0.09 and 0.2029, respectively, whereby it ispossible to obtain an approximately doubled driving current for the samepower supply voltage. When the power supply voltage is further reduced,the present invention will be even more advantageous.

In such a transistor, the gate potential and the potential of theshallow well region coincide with each other, whereby a forward bias isapplied to the pn junction formed between the shallow well region andthe source region (and the drain region). More specifically, in the caseof an n-channel transistor, the potential of the source region is equalto the GND potential, and the potential of the shallow well region isequal to the gate potential. In the case of a p-channel transistor, onthe other hand, the potential of the source region is equal to the powersupply voltage, and the potential of the shallow well region is equal tothe gate potential. In order to prevent a forward current from beingconducted, it is necessary to keep the voltage between the well regionand the source region (or the voltage between the well region and thedrain region) to be less than or equal to the built-in potential of thepn junction. When such a voltage exceeds the built-in potential, theforward current of the pn junction diode is conducted between theshallow well region and the source region (or the drain region). Whenthe potential of the shallow well region is increased to be around thebuilt-in potential, a non-negligible level of pn junction diode forwardcurrent is conducted. Therefore, it is preferred to set the power supplyvoltage so that the potential of the well region is lower than thebuilt-in potential by about 0.1-0.3 V.

FIG. 5 illustrates a semiconductor device according to the secondembodiment of the present invention, wherein: (a) is a plan viewthereof; (b) is a cross-sectional view thereof along b-b′ in (a); (o) isa cross-sectional view thereof along c-c′ in (a); and (d) is across-sectional view thereof along d-d′ in (a). In the figure, membersthat provide similar functions to those of FIG. 1 are provided with likereference numerals.

The device of the second embodiment corresponds to the device of claim1.

The transistor of the second embodiment comprises: a deep well region102 provided in an Si semiconductor substrate 101; a shallow well region103 provided in the deep well region 102, the shallow well region 103being shallower than the deep well region 102 and having the oppositeconductivity type to that of the deep well region 102; a source region107 and a drain region 107 provided in the shallow well region 103, thesource region 107 and the drain region 107 having the oppositeconductivity type to that of the shallow well region 103, i.e., the sameconductivity type as that of the deep well region 102; and a gateelectrode 106 overlying the channel region between the source region 107and the drain region 107 via a gate insulation film 105, therebyproviding a transistor comprising the source region 107, the drainregion 107 and the gate electrode 106.

This embodiment is characterized in that the gate electrode 106 of thetransistor is electrically connected to the shallow well region 103 viaa contact hole 108. The embodiment is also characterized in that theshallow well region 103 is electrically separated from an adjacentshallow well region comprising another semiconductor device.

As in the first embodiment, the shallow well region 103 has a structurein which a high concentration region 111 is sandwiched between lowconcentration regions 112 so as to reduce the resistance of the shallowwell region 103.

With such a structure, it is possible to realize a dynamic thresholdoperation without using an SOI (Silicon On Insulator) substrate.

FIGS. 6 and 7 illustrate a relationship between the gate potential andthe driving current of the transistor of the second embodiment. As Joapparent from the figure, the gradient of a curve in the sub-thresholdregion (an amount of change in the gate potential required to increasethe driving current by an order of magnitude) is about 60 mV/dec. Withthis transistor, It is possible to obtain a large driving current by asmall change in the gate potential as compared to the gradient of acurve in the sub-threshold region of an ordinary MOSFET (80 mV/dec-100mV/dec).

In the second embodiment, the impurity concentration of the deep wellregion la set to about 1×10¹⁶/cm³-1×10⁷/cm³, andtheimpurityconcentrationofthe shallow well region is set to5×10¹⁶/cm³-5×10¹⁷/cm³. The depth of the shallow well region is set to500 nm-1500 nm. In the shallow well region, the high concentrationregion 111 is provided so that the concentration has its peak at a depthof 250-600 nm. The peak concentration is 5×10¹⁷/cm³-1×10²¹/cm³.

The impurity concentration of the source region and the drain region isset to be equal to or greater than about 1×10²⁰/cm³, and the junctiondepth is set to 50 nm-300 nm. In order to suppress the short channeleffect of the transistor, the junction depth of the source region andthe drain region should be as small as possible, and the gate insulationfilm should be as thin as possible.

FIG. 8(a) illustrates a variation of the semiconductor device of FIG. 5,wherein: (a) is a plan view thereof; (b) is a cross-sectional viewthereof along b-b′ in (a); (c) is a cross-sectional view thereof alongc-c′ in (a); and (d) is a cross-sectional view thereof along d-d′ in(a).

In this variation, a deep well region 102′ is provided in asemiconductor substrate 101′, and a shallow well region 103′ is providedin the deep well region 102′. The conductivity type of the shallow wellregion 103′ is opposite to that of the deep well region and is the sameas that of the semiconductor substrate 101′.

More specifically, the transistor comprises: a source region and drainregion 107′ provided in the shallow well region; a channel regionprovided between the source region and the drain region; a gateinsulation film 105′ covering the channel region, and a gate electrode106′ provided on the gate insulation film 105′. The gate electrode 106′is electrically connected to the shallow well region 103′ via a contacthole 108′ provided in the gate insulation film 105′.

The illustrated shallow well region 103′ is electrically separated froman adjacent shallow well region (not shown) by a device separation oxidefilm 104′.

In this variation, the device separation oxide film 104′ is also presentbetween a region where the contact between the gate electrode and theshallow well region is provided and a region where the source region andthe drain region are provided.

In the structure as in the second embodiment comprising a shallow wellregion and a deep well region, a parasitic bipolar transistor affectsthe operation of the transistor. This will be described.

FIG. 9 schematically illustrates the layout of the transistor of thepresent invention and parasitic bipolar transistors. A case of ann-channel MOS transistor and parasitic npn bipolar transistors will bedescribed below, though a case of a p-channel MOS transistor andparasitic pnp bipolar transistors can also be considered to beequivalent to this but with the polarities being symmetrically opposite(reversed).

In the MOS transistor (referred to as a “main transistor”), the sourceregion is connected to GND, the gate electrode to an input V_(IN), andthe drain region to an output V_(OUT). It is assumed that the potentialof the shallow well region is V_(s-well), and the potential of the deepwell region is V_(d-well).

In the main transistor as illustrated in FIG. 9, three parasitic bipolartransistors, indicated respectively by Tr1, Tr2 and Tr3 are formed inaddition to the main transistor. Table 1 below shows directions ofrespective operating currents of these parasitic bipolar transistor.

TABLE 1 Initial value Direction of OUT of current Direction DirectionDirection before of of current of current of current V_(d-Well) input INMOSFET of Tr1 of Tr2 of Tr3 VDD VDD VDD ← ← ◯ ↑ Δ ↑ X GND OFF OFF OFFOFF GND VDD OFF OFF ↑ Δ ↑ X GND OFF OFF OFF OFF GND VDD VDD ← ← ◯ OFF ↓◯ GND OFF OFF OFF OFF GND VDD OFF OFF OFF OFF GND OFF OFF OFF OFF

The direction of each arrow in Table 1 indicating the direction of acurrent corresponds to the direction of an arrow in FIG. 9. The symbol“∘” used in Table 1 indicates that the transistor operates to assist theoperation of the main transistor; the symbol “Δ” indicates that thetransistor causes a leak current which is irrelevant to the operation ofthe main transistor; and the symbol “X” indicates that the transistoroperates to hamper the operation of the main transistor.

For example, when the potential (V_(d-well)) of the deep well region isfixed to the level of the power supply voltage (V_(DD)), and a voltageV_(DD) is input to the gate electrode, the parasitic bipolar transistorTr3 operates to hamper the operation of the main transistor. In otherwords, while the main transistor is operating to make (keep) the output(V_(out)) to be GND, the parasitic bipolar transistor Tr3 operates tomake (keep) the output (V_(out)) to be the power supply voltage V_(DD).In this case, the parasitic bipolar transistor Tr2 operates to generatea leak current which is irrelevant to the device operation.

Therefore, when the potential (V_(d-well)) of the deep well region isfixed to the power supply voltage (V_(DD)), it is necessary to designthe device so that an excessive current is not conducted through theparasitic bipolar transistors Tr2 and Tr3. According to an experimentconducted by the present inventors, the current of the parasitic bipolartransistor could be suppressed to a negligible level with respect to theON current of the main transistor, by setting the base width of theparasitic bipolar transistors Tr2 and Tr3 to be equal to or greater than200 nm, while setting the impurity concentration of the base portion tobe less than or equal to 2×10¹⁷/cm³. Herein, the base width means adistance from the lower end of the source region and the drain region tothe lower end of the shallow well region.

When the potential (V_(d-well)) applied to the deep well region is setto the GNP level, the parasitic bipolar transistor operates in a way toassist the main transistor for any input/output relationship. In thiscase, the main transistor can conduct a current equal to the sum of thecurrent of the main translator and the current of the parasitic bipolartransistor. Therefore, when the operation of the parasitic bipolartransistor is positively adopted, it is possible to obtain an evengreater driving power than that obtained by the main transistor alonewhich does not exhibit the operation of the parasitic bipolartransistor.

FIG. 10 schematically illustrates a semiconductor device according tothe third embodiment of the present invention, wherein: (a) is a planview thereof: (b) is a cross-sectional view thereof along b-b′ in (a);(a) is a cross-sectional view thereof along c-c′ in (a): and (d) is across-sectional view thereof along d-d′ in (a).

The device of the third embodiment corresponds to the device of claim 2.

The transistor of the third embodiment is an improvement to the secondembodiment. In particular, when assuming that a plurality of transistorsare to be formed on the same substrate according to the secondembodiment, the adjacent transistors are to be separated by a deviceseparation oxide film 104 (a general field oxide film). In such a case,however, the junction depth of the well region is deeper than the fieldoxide film. Therefore, in order to prevent shallow well regions ofadjacent transistors from overlapping each other due to the diffusionbetween these shallow well regions, it is necessary to increase theseparation width between the shallow well regions. Accordingly, theseparation region becomes very large, thereby increasing the area on thesemiconductor substrate to be occupied by a single transistor. This isnot suitable for miniaturization.

In view of this, according to the third embodiment, the separationregion is provided in the form of a groove-shaped separation regionwhich is deeper than the shallow well region but shallower than the deepwell region.

As is apparent from FIG. 10, the transistor according to the thirdembodiment comprises: a deep well region 302 provided in a semiconductorsubstrate 301; a shallow well region 303 provided on the deep wellregion 302, the shallow well region 303 being shallower than the deepwell region 302 and having the opposite conductivity type to that of thedeep well region 302; a source region 307 and a drain region 307provided in the shallow well region 303, the source region 307 and thedrain region 307 having the opposite conductivity type to that of theshallow well region 303, i.e., the same conductivity type as that of thedeep well region 302; and a gate electrode 306 overlying the channelregion between the source region 307 and the drain region 307 via a gateinsulation film 305, thereby providing a transistor comprising thesource region 307, the drain region 307 and the gate electrode 306.

This transistor is characterized in that the gate electrode 306 iselectrically connected to the shallow well region 303 via a contact hole308.

The transistor is also characterized in that a groove-shaped separationregion 304 is provided between the shallow well region 303 and anothershallow well region of an adjacent transistor, so that the shallow wellregions are electrically separated from each other by the groove-shapedseparation region 304.

Moreover, in order to reduce the resistance of the shallow well region303, the shallow well region 303 has a structure in which a highconcentration region 311 is interposed between low concentration regions312.

Furthermore, a high impurity concentration region 321 having the sameconductivity type as that of the deep well region 302 is provided so asto electrically connect the upper metal lines (not shown) with the deepwell region 302 and to obtain an ohmic connection between the metallines and the semiconductor substrate 301.

Reference numeral 331 denotes a high impurity concentration regionhaving the same conductivity type as that of the shallow well region303; 341 denotes a field oxide film; 361 denotes a silicide film; 308denotes a contact hole for connecting the gate electrode 306 to theshallow well region 303; 309 denotes a contact hole for connecting theupper metal lines to the source region 307 and the drain region 307: and310 denotes a contact hole for connecting the deep well region 302 tothe upper metal lines.

A contact hole for connecting the gate electrode 306 to the upper metallines, though not shown, may be provided on the contact hole 308 forconnecting the gate electrode 306 to the shallow well region 303.

In the third embodiment, the respective depths and concentrations of thewell regions 302 and 303 are similar to those in the second embodiment.The depth of the groove-shaped separation region 304 may be set to beequal to or greater than the sum of the depth of the shallow well region303 and the width of a depletion layer which is formed by the junctionbetween the shallow well region 303 and the deep well region 302 (moreaccurately, a length of the depletion layer depth which extends on theside of the deep well region 302). In this way, the respective shallowwell regions 303 of adjacent transistors can be electrically separatedfrom each other. If the depletion layer exceeds the depth of thegroove-shaped separation region 304, the depletion layers of theadjacent transistors are connected to each other, thereby resulting in apunch-through between the adjacent shallow well regions 303.

In such a structure, the adjacent transistors are separated from eachother only by the space of the groove-shaped separation region 304(typically, a minimum process dimension), whereby it is possible torealize a transistor capable of dynamic threshold operation using a bulksemiconductor substrate, without using an SOI substrate, and withoutsacrificing the integration concentration.

Now, the structure of the contact hole 308 for obtaining an ohmicconnection between the gate electrode 306 and the shallow well region303 in the transistor of the third embodiment will be described.

In a buried channel type transistor, the gate electrode and the shallowwell region have the same conductivity type, whereby an ohmic connectioncan be obtained even when a contact hole is provided in the gateinsulation film for direct connection therebetween. In a surface channeltype transistor, however, the electrode and the shallow well region havethe opposite conductivity types, whereby when they are directlyconnected together, a PN junction is formed and an ohmic contact cannotbe obtained.

In view of this, according to the third embodiment, the metal silicidefilm 361 and the high impurity concentration region 331 having the sameconductivity type as that of the shallow well region 303 are providedbetween the gate electrode 306 and the shallow well region 303 so thatthe gate electrode 306 and the shallow well region 303 can be connectedto each other with an ohmic connection irrespective of the conductivitytype of the gate electrode 306 and the shallow well region 303. Inparticular, the elements are connected in the following order: the gateelectrode 306→the metal silicide film 361→the high impurityconcentration region 331 having the same conductivity type as that ofthe shallow well region 303 →the shallow well region 303,

In such a structure, by setting the impurity concentration of the highimpurity concentration region 331 to be equal to or greater than1×10²⁰/cm³, it is possible to obtain an ohmic connection between themetal silicide film 361 and the shallow well region 303 (since the gateelectrode 306 originally has a high concentration (typically, 1×10²⁰/cm³or greater), it can be ohmically connected to the metal silicide film361).

If the silicide film is directly connected to the shallow well region303 without providing the high impurity concentration region 331 havingthe same conductivity type as that of the shallow well region 303, theconnection will be a metal semiconductor Schottky connection, whereby anohmic connection cannot be obtained.

A specific method for connecting the gate electrode 306 to the shallowwell region 303 is to form an oxide film on a side wall of the gateelectrode 306, then open the contact hole 308 in a desired region of thegate electrode 306 so as to run from the gate electrode 306 to theshallow well region 303, and perform a salicidation process. Inparticular, after the contact hole 308 is provided running from the gateelectrode 306 to the shallow well region 303, a high melting metal isdeposited therein, followed by a heat treatment to effect a reactiontherebetween. In a region where the high melting metal is in contactwith silicon, a silicide film is formed in a self-alignment manner,while a silicide film is also formed in the contact hole 308 runningfrom the gate electrode 306 to the shallow well region 303, therebyelectrically connecting the gate electrode 306 to the shallow wellregion 303. This phenomenon is based on a lateral growth of a silicidefilm. Since the gate insulation film is very thin (3-5 nm in thisembodiment), the silicide film formed on the bottom (shallow well region303) of the contact hole 308 is connected to the silicide film connectedon the side wall (gate polycrystal silicon) of the contact hole 308.Moreover, ion implantations into the source region 307, the drain region307, the gate electrode 306, and a contact between the gate electrode306 and the shallow well region 303 may be performed either before orafter the silicidation reaction. Alternatively, when forming acomplementary device which will be described later, an ion implantationinto a contact between the gate electrode 306 and the shallow wellregion 303 may be performed while performing an ion implantation intothe source region and the drain region of the transistor having theopposite conductivity type.

FIG. 11 schematically illustrates a semiconductor device according tothe fourth embodiment of the present invention, wherein: (a) is a planview thereof; and (b) is a cross-sectional view thereof along b-b′ in(a). In the figure, members that provide similar functions to those ofthe device illustrated in FIG. 10 are provided with like referencenumerals.

The device of the fourth embodiment corresponds to the device of claim5, and is a complementary circuit based on the semiconductor device ofthe third embodiment. The device comprises a p-channel area 371 in whichp-channel transistors are arranged, and an n-channel area 372 in whichn-channel transistors are arranged.

In the p-channel area 371, the n-type shallow well regions 303 areprovided in the p-type deep well region 302 so as to be separated fromone another by the groove-shaped separation region 304, and n-channeltransistor devices are provided in the respective shallow well regions303.

Similarly, in the n-channel area 372, the p-type shallow well regions303 are provided in the n-type deep well region 302 so as to beseparated from one another by the groove-shaped separation region 304,and n-channel transistor devices are provided in the respective shallowwell regions 303.

While a field oxide film as in the second embodiment can be used asmeans to separate the shallow well regions 303 from one another, it ispreferred for suppressing the lateral extension of the shallow wellregion 303 to provide the separation with a groove-shaped separationregion which is deeper than the shallow well region but shallower thanthe deep well region as illustrated in the third embodiment. Thus, thegroove-shaped separation region is employed again in the fourthembodiment.

In this embodiment, the p-type deep well region and the n-type deep wellregion are in contact with each other. Therefore, it is necessary toground the p-type deep well region to GND and to fix the n-type deepwell region to the power supply voltage so that reverse biases resultwhen applying bias voltages to the respective deep well regions (whenthe voltages are set so that a forward bias results, a forward currentirrelevant to the device operation will be continuously conducted).

As described above, in view of the operation of the vertical parasiticbipolar transistor formed of the shallow well region 303 as a base andthe deep well region 302 as a collector (emitter), rather than thesource region 307 and the drain region 307, the operation of the maintransistor is hampered by the vertical parasitic bipolar transistor.Therefore, when a complementary circuit is implemented as in the fourthembodiment, it is necessary to set the depth (related to the base width)and the concentration of the shallow well region 303 so that thevertical parasitic bipolar transistor has a gain which is as close to 1as possible (i.e., so that the base current and the emitter current areequal to each other). In the fourth embodiment, the depth and theconcentration of each well region are set as in the third embodiment.

In view of the short channel effect, variations in the threshold, etc.,a surface channel type transistor is preferred which comprises a sourceregion, a drain region and a gate electrode of the same conductivitytype. In such a case, an impurity is typically introduced by an ionimplantation method simultaneously into the source region, the drainregion and the gate electrode.

In the complementary circuit of the fourth embodiment, the introductionof an impurity into the source region, the drain region and the gateelectrode of the n-channel transistor and the introduction of animpurity into the contact area between the gate electrode and theshallow well region of the p-channel transistor are simultaneouslyperformed in a single ion implantation process. Moreover, theintroduction of an impurity into the source region, the drain region andthe gate electrode of the p-channel transistor and the introduction ofan impurity into the contact area between the gate electrode and theshallow well region of the n-channel transistor are simultaneouslyperformed in a single ion implantation process. Thus, the process issimplified.

In such a surface channel type transistor, the conductivity type of thewell region and the conductivity type of the gate electrode are oppositeto each other, and they cannot be electrically connected to each otherdirectly. Thus, as described above, semiconductor layers of the oppositeconductivity types can be connected to each other using a salicide filmfor the gate electrode. Since the impurity concentration of the shallowwell region is low, an ohmic contact is obtained between the silicidefilm and the shallow well region by introducing an impurity of a highconcentration having the same conductivity type as that of the shallowwell region into the contact region.

For the purpose of carrying out the present invention, the transistor isnot necessarily limited to those of the surface channel type. Rather,the present invention can be carried out with a buried channel typetransistor (where the source region and the drain region have theopposite conductivity type to that of the gate electrode), a metal gate(a tungsten gate, an aluminum gate, a molybdenum gate, a nitridetitanium gate, a titanium-tungsten gate, etc.) or with a multilayer filmgate comprising the above-described metal and a polysilicon.

FIG. 12 is a cross-sectional view illustrating a variation of the fourthembodiment.

The transistor of this variation corresponds to claim 3.

In this variation, the deep well region 302 is provided in a deeper wellregion 381 having the opposite conductivity type to that of the deepwell region 302, and the deep well region 302 and the deeper well region381 are set to the same potential.

Between adjacent transistors, an n-type deeper well region 381 and ap-type deeper well region 381 are in contact with each other. Therefore,the n-type deeper well region 381 is set to the power supply voltage(i.e., the p-type deep well region 302 is set to the power supplyvoltage) and the p-type deeper well region 381 is grounded to GND (i.e.,the n-type deep well region is grounded to GND) so that the respectivedeeper well regions 381 and 381 are reversely biased. Then, the verticalparasitic bipolar transistor operates in a way to assist the operationof the main transistor.

Thus, the variation can solve the problem existing in theabove-described fourth embodiment, i.e., the vertical parasitic bipolartransistor hampering the operation of the main transistor.

FIG. 13 is a cross-sectional view illustrating an alternative variationof the fourth embodiment.

A transistor of this alternative variation corresponds to the device ofclaim 4.

In this variation, in order to reduce the separation region between deepwell regions and to reduce the boundary rule, thereby reducing theoccupied area, a groove-shaped separation region 382 is provided forseparating the respective deep well regions 302 of adjacent transistors.The groove-shaped separation region 382 is deeper than the sum of thedepth of the deep well region 302 and the width of a depletion layerwhich is formed by the junction between the deep well region 302 and thedeeper well region 381, and is shallower than the deeper well region381.

FIG. 14 schematically illustrates a semiconductor device according tothe fifth embodiment of the present invention, wherein: (a) is a planview thereof; and (b) is a cross-sectional view thereof along b-b′ in(a).

The device of the fifth embodiment corresponds to the device of claim 6,and improves the freedom in the arrangement of the n-channel transistorsand the p-channel transistors while maintaining the restriction as inthe complementary circuit of the fourth embodiment, i.e., the limitationthat transistors of the same conductivity type are arranged in one typeof deep well region.

In this device, a groove-shaped separation region 502 is provided in asemiconductor substrate 501 of a p type, for example, and a plurality ofactive regions are provided surrounded by the groove-shaped separationregion 502.

A translator having a source region and a drain region of the oppositeconductivity type to that of the semiconductor substrate 501 (ann-channel transistor in this case) is provided in one of the activeregions surrounded by the groove-shaped separation region 502 where adeep well region 503 of the opposite conductivity type to that of thesemiconductor substrate 501 (an n-channel deep well region in this case)exists. In this active region, a shallow well region 504 of the sameconductivity type as that of the semiconductor substrate 501 (a p-typeshallow well region in this case) is provided on the deep well region503, and a source region 505 and a drain region 505 having the oppositeconductivity type to that of the semiconductor substrate 501 (n-typesource region and drain region) are provided in the shallow well region504, while a gate electrode 506 is electrically connected to the shallowwell region 504.

A transistor having a source region and a drain region of the sameconductivity type as that of the semiconductor substrate 501 (ap-channel transistor in this case) is provided in one of the activeregions where a deep well region does not exist. In this active region,a shallow well region 507 of the opposite conductivity type to that ofthe semiconductor substrate 501 (an n-type shallow well region in thiscase) is provided, and a source region 508 and a drain region 508 havingthe same conductivity type as that of the semiconductor substrate 501(p-type source region and drain region) are provided in the shallow wellregion 507, while a gate electrode 509 is electrically connected to theshallow well region 507 (an n-type shallow well region in this case).

The transistor having the source region and the drain region of theopposite conductivity type to that of the semiconductor substrate 501and the transistor having the source region and the drain region of thesame conductivity type as that of the semiconductor substrate 501together form a complementary circuit.

For a p-type semiconductor substrate 501, it is grounded to GND. Whenusing an n-type semiconductor substrate 501, the conductivity types ofthe respective regions illustrated above may be reversed, and thesemiconductor substrate 501 may be set to the power supply voltage.Moreover, the deep well region 503 having the opposite conductivity typeto that of the semiconductor substrate 501 has a potential which is notfixed and thus is floating. The potential can be fixed for higherresistance to the influence of the external noise.

Reference numeral 511 denotes a contact hole for connecting the sourceregion and the drain region to the upper metal lines.

In the fifth embodiment, as in the third embodiment, the gate electrodes506 and 509 are connected to the respective shallow well regions 504 and507 via a silicide film 510 at the position of the contact hole 513. Asin the third embodiment, a high concentration region (not shown) may beprovided between a silicide film 513 and the shallow well region 507 inorder to obtain an ohmic connection between the silicide film 513 andthe low concentration shallow well region 507. The connection at thisposition is not limited to the way illustrated above. It isalternatively possible to provide a contact hole running through thegate electrode and reaching the shallow well region before the uppermetal line process, with the connection being made by metal lines.

Although the deep well region 503 of the opposite conductivity type tothat of the substrate (an n-type deep well region in this case) isfloating, the n-type shallow well region 507 and the p-type shallow wellregion 504 are completely separated from each other by the groove-shapedseparation region 502. Therefore, a feedback circuit such that acollector current of a parasitic bipolar transistor of one of theshallow well regions provides a base current of a parasitic bipolartransistor of the other shallow well region is not formed, so thatlatch-up does not occur.

In this embodiment, since a p-type semiconductor substrate 501 is used,a vertical stack is provided in the n-channel transistor comprising then-type source region 505 and drain region 505, the p-type shallow wellregion 504, the deep well region 503 (floating), and the p-typesemiconductor substrate 501, thus forming a parasitic thyristor therein.However, the biasing conditions for a complementary circuit are providedso that the n-type source region is grounded to GND, and the p-typesemiconductor substrate is also grounded to GND via a contact hole 512,whereby the parasitic thyristor is not turned ON (no latch-up).

With such a structure, the n-channel transistor and the p-channeltransistor can be freely arranged without being bound by the boundaryrule, thereby increasing the freedom in design.

The depth including the width of the depletion layer which is formed bythe junction between the deep well region 503 (an n-type deep wellregion in this case) and the semiconductor substrate 501 should notexceed that of the groove-shaped separation region 502. Of course, thedepth including the width of the depletion layer which is formed by thejunction between the n-type shallow well region 507 and thesemiconductor substrate 501 also should not exceed that of thegroove-shaped separation region 502.

FIG. 15 schematically illustrates a semiconductor device according tothe sixth embodiment of the present invention, wherein: (a) is a planview thereof; and (b) is a cross-sectional view thereof along b-b′ in(a).

The device of the sixth embodiment corresponds to the device of claim 7,and is intended to improve the freedom in the arrangement of then-channel transistors and the p-channel transistors as in the fifthembodiment.

The device comprises: a deeper well region 611 (p-type in this case)provided in a semiconductor substrate 601; and a groove-shapedseparation region 602 provided in the deeper well region 611, wherein aplurality of active regions are formed to be surrounded by thegroove-shaped separation region 602.

As in the fifth embodiment, either one of the two types of transistorsof the complementary circuit is provided in each of the active regions.In particular, one type of transistor comprises an n-type deep wellregion 603, a p-type shallow well region 604, and an n-type sourceregion 605 and drain region 605 provided in an active region, The othertype of transistor comprises an n-type shallow well region 607, and ap-type source region 608 and drain region 608 provided in an activeregion.

Conversely, when forming an n-type deeper well region 611, a p-type deepwell region, an n-type shallow well region, and a p-type source regionand drain region may be provided in an active region, while forming ap-type shallow well region, and an n-type source region and drain regionin another active region.

The gate electrodes 606 and 609 are electrically connected to thecorresponding shallow well regions 604 and 607, respectively, via acontact hole 613.

Reference numeral 610 denotes a silicide film, 611 denotes a contacthole for connecting the source region and drain region to the uppermetal lines, and 612 denotes a contact hole for connecting thesemiconductor substrate 601 to the upper metal lines.

In this embodiment, the deeper well region 611 is set to a constantpotential. Since the deeper well region 611 is of p type, the deeperwell region 611 may be grounded to GND via the contact hole 612.

The device of the sixth embodiment as described above has a structure inwhich the deeper well region 611 is additionally provided to thesemiconductor substrate of the fifth embodiment, where it is possible tofreely set the concentration of the deeper well region 611.

The potential of the deep well region 603 is not fixed but floating.Therefore, the potential may be fixed for higher resistance to theinfluence of the external noise.

The latch-up can be treated a(in the fifth embodiment. With thisstructure, the n-channel transistor and the p-channel transistor can befreely arranged without being bound by the boundary rule, therebyincreasing the freedom in design.

FIG. 16 schematically illustrate a semiconductor device according to theseventh embodiment of the present invention, wherein; (a) is a plan viewthereof; and (b) is a-cross-sectional view thereof along b-b′ in (a).

The device of the seventh embodiment corresponds to the device of claim8, and is intended to improve the freedom in the arrangement of then-channel transistors and the p-channel transistors as in the fifthembodiment.

The device comprises a groove-shaped separation region 702 in asemiconductor substrate 701 (p type in this case), wherein a pluralityof active regions are formed to be surrounded by the groove-shapedseparation region 702.

As in the fifth embodiment, either one of the two types of transistorsof the complementary circuit is provided in each of the active regions.In particular, one type of transistor comprises an n-type deep wellregion 703, a p-type shallow well region 704, and an n-type sourceregion 705 and drain region 705 provided in an active region. The othertype of transistor comprises a p-type deep well region 707, an n-typeshallow well region 708, and a p-type source region 709 and drain region709 provided in an active region.

The gate electrodes 706 and 710 are electrically connected to thecorresponding shallow well regions 704 and 707, respectively, via acontact hole 714. Reference numeral 712 denotes a contact hole forconnecting the source region and drain region to the upper metal lines.

In this embodiment, the semiconductor substrate 701 is provided with aconstant potential via a contact hole 713. Since the semiconductorsubstrate 701 is of p type, the semiconductor substrate 701 may begrounded to GND. Then, the deep well region 707 of the same conductivitytype as that of the p-type semi-conductor substrate 701 is also grounded(in the case of n type, it may be set to the power supply voltage).

The deep well region 703 of the opposite conductivity type to that ofsemiconductor substrate 701 has a potential which is not fixed and thusis floating. The potential can be fixed for higher resistance to theInfluence of the external noise.

The latch-up can be treated as in the fifth embodiment, with thisstructure, the n-channel transistor and the p-channel transistor can befreely arranged without being bound by the boundary rule, therebyincreasing the freedom in design.

FIG. 17 illustrates a variation of the seventh embodiment, wherein: (a)is a plan view thereof; and (b) is a cross-sectional view thereof alongb-b′ in (a).

In the seventh embodiment, the deep well region 703 of the oppositeconductivity type to that of semiconductor substrate 701 is floating. Inview of this, the variation comprises a structure for guiding the deepwell region 703 to the surface of the semiconductor substrate 701 forfixing the potential thereof.

In particular, a deep groove-shaped separation region 721 is provided inthe semiconductor substrate 701, and an active region is provided to besurrounded by the deep groove-shaped separation region 721. A shallowgroove-shaped separation region 722 is provided in the deep well region703 in the active region so that the active region is divided into tworegions by the shallow groove-shaped separation region 722, wherein theshallow well region 704 is provided in one of the regions, while thedeep well region 703 is guided to the surface of the semiconductorsubstrate 701 in the other region.

Reference numeral 724 denotes a contact hole for connecting the gateelectrode and the upper metal lines, and 725 denotes a contact hole forconnecting the deep well region 703 to the upper metal lines.

In the transistors of the above-described embodiments, it is necessaryto set the following conditions in order to assure an appropriateoperation thereof.

Basically, a depletion layer formed by one pn junction should not beconnected to another depletion layer formed by another pn junction. Forexample, assume that a transistor on a p-type semiconductor substratecomprises an n-type source region and drain region, a p-type shallowwell region, and an, n-type deep well region, wherein the structure downto the n-type deep well region is separated by a groove-shapedseparation region. In such a case, the depletion layer formed by thejunction between the n-type source region and drain region and thep-type shallow well region should not be connected to the depletionlayer formed by the junction between the p-type shallow well region andthe n-type deep well region. If they are connected to each other, then-type source region and drain region and the n-type deep well regionwill be punched through and electrically connected together.

Moreover, the depletion layer formed by the junction between the n-typesource region and the p-type shallow well region should not be connectedto the depletion layer formed by the junction between the n-type drainregion and the p-type shallow well region. If they are connected to eachother, a punch-through occurs between the source region and the drainregion.

Furthermore, the depletion layer formed by the junction between then-type deep well region and the p-type semiconductor substrate shouldnot be connected to the depletion layer formed by the junction betweenanother n-type region (i.e., an n-type deep well region of an adjacenttransistor) and the p-type semiconductor substrate. Therefore, the depthof the groove-shaped separation region should be greater than the depthof the n-type deep well region including the depletion layer (the sum ofthe depth of the n-type deep well region and the width extending underthe depletion layer formed by the junction between the deep well regionand the p-type semiconductor substrate).

In particular, it is necessary to determine the respective depths of thesemiconductor layer regions and the depth of the groove-shapedseparation region so as to satisfy the condition that a depletion layerformed by one pn junction not be connected to another depletion layerformed by another pn junction. Since the width of the depletion layer isdetermined by the mutual relationship among the respectiveconcentrations of the semiconductor layers, these depths cannot bedetermined uniquely. However, a basic operation of a transistor can besatisfied as long as the above-described condition is met, Therefore,after the condition is met, the resistance and the concentration(related to the parasitic capacitance) of the shallow well region can beused as a guideline for designing the device.

EXAMPLE

Next, a more specific example of the present invention will bedescribed.

As described above, the present invention has an objective of realizinga dynamic threshold operation based on the use of a bulk semiconductorsubstrate, and the present invention is based on the use of a wellregion of a bulk semiconductor substrate in place of the body of aconventional SOI substrate which has been considered to be problematicbecause of its high resistance.

Irrespective of whether a bulk semiconductor substrate or an SOIsubstrate is used, there is an upper limit to the impurity concentrationof the channel region, which is related to the threshold as describedabove. Moreover, an SOI substrate has a small body thickness, and thus avery high resistance.

On the contrary, in the present invention, there is no particular limitto the depth of a well region in a bulk semiconductor substrate, and theconcentration of a region irrelevant to the channel region can beincreased as desired while keeping a low concentration of the channelregion. Thus, the resistance of the well region (corresponding to thebody of an SOI substrate) can be reduced (although, ultimately, thedepth of the well region can be increased by the thickness of thesemiconductor substrate, it can be increased only to about 5 μm to be ina commonly acceptable range, because the groove-shaped separation regionhas to be even deeper).

At a position where the source region and drain region are in contactwith the shallow well region, the junction capacitance should be made assmall as possible (the capacitance should be small because the speed ofa circuit is determined by the amount of current flowing therethroughand the CR time constant), and the concentration of a well region at thecontact position should preferably be as low as possible. Also for theconcentration of the deep well region or the shallow well region on theside contacting the semiconductor substrate, the junction capacitancebetween the deep well region and the shallow well region should be assmall as possible, and the concentration of the shallow well regionshould preferably be as low as possible.

In order to further clarify these points, a single transistor having astructure as illustrated in FIG. 18(a) (similar structure to that of thethird embodiment illustrated in FIG. 10) will be illustrated as anexample, and the respective concentrations of the semiconductor layersthereof and the production method therefor will be described below.

In the figure, members that provide similar functions to those of thedevice illustrated in FIG. 10 are provided with like reference numerals.

In this example, the depth d1 of the source region 307 and drain region307 may be set to 50-200 nm, the peak concentration of the regions 307to 1×10¹⁹/cm³ or greater (preferably, 1×10²⁰/cm³ or greater), the depthd2 of the upper low impurity concentration region 312 in the shallowwell region 303 to 100-500 nm from the surface of the semiconductorsubstrate 301 (as described above, the depletion layer d7 extending fromthe source region 307 and the drain region 307 is preferably so deepthat it does not overlap the high concentration region 311), theconcentration of the high concentration region 312 to 1×10¹⁶-1×10¹⁸/cm³(preferably, 1×10¹⁶-2×10¹⁷/cm³ when the concentration of the well regionis too low, it is necessary to increase the concentration thereof in thevicinity of the channel in order to control the threshold), and the peakconcentration of the high concentration region 311 in the shallow wellregion 303 to 5×10¹⁷/cm³ or greater (possibly, about 1×10²¹-1×10/cm³, acommonly acceptable upper limit).

For the production method, the simplest way is to form the shallow wellregion 303 of a uniform concentration (a high temperature annealingprocess at about 1000° C.-1100° C. can be performed after the ionimplantation), and then to form the high concentration region 311 by anion Implantation method. Although it depends upon the injection energy,the concentration can be set so that the peak concentration will existin the range (200-700 nm) of the depth d3 from the semiconductorsubstrate 301 to be within a commonly acceptable range. Alternatively,it is possible to perform a number of (commonly, 2 to 3) injections withvaried injection energies so that the high concentration region 311exists in a wide range in the depth direction.

While depth d4 down to the lower region 312 of low concentration in theshallow well region 303 (the depth reaching the deep well region 302)depends upon the depth of the groove-shaped separation region 304, thedepth d4 may be about 300-3000 nm to be in a commonly acceptable range.Moreover, the concentration thereof may be the same as that of the upperregion 312 of low concentration (of course, the concentration graduallylowers in the depth direction, and a junction isbasically formed at aposition where the concentration is equal to the impurity concentrationof the deep well region 302). The concentration of the deep well region302 may be set to about 1×10¹⁶/cm³-1×10⁷/cm³.

As a specific example, a transistor was provided while setting the depthd4 of the shallow well region 303 from the surface of the semiconductorsubstrate 301 to 1.0 μm, the concentration of the low concentrationregion 312 to 5×10¹⁶/cm³-8×10¹⁶/cm³, the peak concentration of the highconcentration region 311 to 5×10¹⁸/cm³-8×10₁₈/cm³, the depth d3 of thepeak position from the surface of the semiconductor substrate 301 to 600nm, the concentration of the deep well region 302 to 5×10¹⁶/cm³, thedepth of the groove-shaped separation region 304 to 1.6 μm, and thethickness of the gate oxide film to 3 nm. In this transistor, at a powersupply voltage of 0.5 V, ON currents of 0.2-0.25 mA (NMOS; gate length:0.1 μm) and 0.08-0.13 mA (PMOS: gate length: 0.13 μm) were achieved, andthe apparent threshold was 0.10-0.15 V. A ring oscillator using thecomplementary inverter had a propagation delay time of about 30 psec perstage.

FIGS. 18(b) and 18(c) each show an effective carrier concentration alonga-a′ in FIG. 18(a). FIG. 18(b) and 18(a) respectively show profiles forrelatively higher and lower concentrations of the high concentrationregion 311 in the shallow well region 303.

In this embodiment, the high impurity concentration region 311 issandwiched between the low impurity concentration regions 312. As isapparent from FIGS. 18(b) and 18(c), the actual structure is designed sothat the impurity concentration changes continuously, and the peakconcentration of the high concentration region 311 will exist around300-700 nm from the surface, for example, resulting in a structure inwhich the concentration is gradually decreased toward the boundarybetween the surface of the semiconductor substrate 301 and the deep wellregion. Therefore, there is no well-defined boundary between the highconcentration region 311 and the low concentration regions 312.

In this embodiment, the well regions are formed by an ion implantationmethod. For example, the shallow well region 303 in which theconcentration transients as follows from the surface of thesemiconductor substrate 301: low concentration→high concentration lowconcentration, can be provided by: performing an injection at a low dose(commonly. 2×10¹³/cm³ or less): performing a drive process at atemperature of about 1000° C.-1100° C. (the injection dose, the energy,the drive temperature and the duration are related to the depth of thegroove-shaped separation region 304 and the concentration of the deepwell region 302, and may basically be set to any values as long as therelationship condition with respect to the groove-shaped separationregion 304, which will be described later, is satisfied) so as to formthe shallow well region 303 having a relatively uniform and lowconcentration; and then performing an injection process at a highconcentration (1×10¹³/cm³ or greater) by a high energy injection process(in practice, this can be achieved while oxidizing the gate of thetransistor, and/or while performing an active annealing process for thesource region and drain region).

Now, the relationship among the depth of the groove-shaped separationregion 304, the concentration of the deep well region 302 and theconcentration of the shallow well region 303 will be discussed.Basically, it is necessary that the adjacent shallow well regions 303are electrically separated from each other. In particular, when thedepletion layer at the junction between the shallow well region 303 andthe deep well region 302 is connected to another depletion layer at thejunction between an adjacent shallow well region and an adjacent deepwell region, a punch through occurs between the shallow well regions.Thus, it is necessary to separate them from each other. In order toprevent the punch through, it is necessary to set the depth of thegroove-shaped separation region 304 separating adjacent shallow wellregions from each other to be so deep that the depletion layer at thejunction between the shallow well region 303 and the deep well region302 is not connected to another depletion layer at the junction betweenan adjacent shallow well region and an adjacent deep well region. As aspecific example, when a junction is formed between a shallow wellregion having a depth of about 1 μm and a concentration of about1×10¹⁷/cm³ and a deep well region having a concentration of 5×10/cm³. adepletion layer of about d5=200-250 nm extends from the junction towardthe deep well region, and another depletion layer of about d6=100 nmextends from the junction toward the shallow well region. Therefore, thedepth of the groove-shaped separation region 304 needs to be at leastabout 1.3 μm, and may be designed to a depth of about 1.5-1.7 μm withsome margin.

INDUSTRIAL APPLICABILITY

As is apparent from the above description, in the semiconductor deviceof claim 1, the resistance of the well region corresponds to the bodyresistance of the conventional SOI substrate. The resistance of the wellregion can be made very small, and thus the device can operate at aspeed much higher than that of a DTMOS using the conventional SOIsubstrate.

Moreover, since the shallow well region has a structure in which thehigh impurity concentration region is sandwiched between low impurityconcentration regions, the resistance of the well region can be furtherreduced. With such a structure, it is possible to effectively reduce theresistance of the well region by the high concentration region in themiddle of the shallow well region, while maintaining a low threshold byone of the low concentration regions on the channel side, withoutincreasing parasitic capacitances of the source region and the drainregion (when the impurity concentration of the shallow well region atthe junction between the source region and the drain region is high, thedepletion layer does not sufficiently extend, thereby increasing thejunction capacitance), and without increasing the parasitic capacitancebetween one of the low concentration regions in the shallow well regionexisting on the deeper well region side and the deep well region.

Moreover, in the semiconductor device of claim 3, the deeper well regionis provided between the adjacent deep well regions so as to electricallyseparate the adjacent deep well regions from each other. Particularly,when providing a complementary element having p-type and n-type deepwell regions together on a single semiconductor substrate, the deep wellregions are separated by a deeper well region having an oppositeconductivity type, whereby it is possible to ground the n-type deep wellregion to GND, and to set the p-type deep well region to the powersupply voltage.

Furthermore, the structures of the semiconductor devices of claims 6, 7and 8 are preferred for realizing a complementary circuit, and allow forfree arrangement of n-channel and p-channel elements, without increasingthe area to be occupied by a transistor or having to provide a boundaryrule between the well regions (the n well and the p well must beseparated by at least a certain distance so that latch-up does notoccur).

What is claimed is:
 1. A semiconductor device, comprising: asemiconductor substrate; a deep well region of a first conductivity typeprovided in the semiconductor substrate; a shallow well region of asecond conductivity type provided in the deep well region; a sourceregion and a drain region of the first conductivity type provided in theshallow well region; a channel region provided between the source regionand the drain region; a gate insulation film provided on the channelregion; and a gate electrode provided on the gate insulation film,wherein: the gate electrode is electrically connected to the shallowwell region corresponding to the gate electrode; and the shallow wellregion is electrically separated from an adjacent shallow well regionand has a structure in which a region of a high impurity concentrationis sandwiched between low impurity concentration regions.
 2. Asemiconductor device according to claim 1, wherein the shallow wellregions adjacent to each other are electrically separated from eachother by a groove-shaped separation structure which is deeper than eachof the shallow well regions but shallower than the deep well region. 3.A semiconductor device according to claim 2, wherein the semiconductordevice forms a complementary circuit.
 4. A semiconductor deviceaccording to claim 3, wherein in the shallow well region of thesemiconductor device, a depletion layer formed by a junction between thelow impurity concentration region and the source region and the drainregion is not in contact with the high impurity concentration region. 5.A semiconductor device according to claim 3, wherein the high impurityconcentration region in the shallow well region of the semiconductordevice has an impurity concentration at its peak position in aconcentration range of 1×10²¹/cm³-5×10¹⁷/cm³.
 6. A semiconductor deviceaccording to claim 3, wherein the low impurity concentration region inthe shallow well region of the semiconductor device has an impurityconcentration in a concentration range of 1×10¹⁸/cm³-1×10¹⁶/cm³.
 7. Asemiconductor device according to claim 2, wherein in the shallow wellregion of the semiconductor device, a depletion layer formed by ajunction between the low impurity concentration region and the sourceregion and the drain region is not in contact with the high impurityconcentration region.
 8. A semiconductor device according to claim 2,wherein the high impurity concentration region in the shallow wellregion of the semiconductor device has an impurity concentration at itspeak position in a concentration range of 1×10²¹/cm³-5×10¹⁷/cm³.
 9. Asemiconductor device according to claim 2, wherein the low impurityconcentration region in the shallow well region of the semiconductordevice has an impurity concentration in a concentration range of1×10¹⁸/cm³-1×10¹⁶/cm³.
 10. A semiconductor device according to claim 1,wherein the semiconductor device forms a complementary circuit.
 11. Asemiconductor device according to claim 1, wherein in the shallow wellregion of the semiconductor device, a depletion layer formed by ajunction between the low impurity concentration region and the sourceregion and the drain region is not in contact with the high impurityconcentration region.
 12. A semiconductor device according to claim 1,wherein the high impurity concentration region in the shallow wellregion of the semiconductor device has an impurity concentration at itspeak position in a concentration range of 1×10²¹/cm³-5×10⁷/cm³.
 13. Asemiconductor device according to claim 1, wherein the low impurityconcentration region in the shallow well region of the semiconductordevice has an impurity concentration in a concentration range of1×10¹⁸/cm³-1×10¹⁶/cm³.
 14. A semiconductor device, comprising: asemiconductor substrate; a deeper well region of a first conductivitytype provided in the semiconductor substrate; a deep well region of asecond conductivity type provided in the deeper well region; a shallowwell region of the first conductivity type provided in the deep wellregion of the second conductivity type; a source region and a drainregion of the second conductivity type provided in the shallow wellregion; a channel region provided between the source region and thedrain region; a gate insulation film provided on the channel region; anda gate electrode provided on the gate insulation film, wherein: the gateelectrode is electrically connected to the shallow well regioncorresponding to the gate electrode; the deep well region and theshallow well region are electrically separated respectively from anadjacent deep well region and an adjacent shallow well region; and theshallow well region has a structure in which a high impurityconcentration region is sandwiched between low impurity concentrationregions.
 15. A semiconductor device according to claim 14, wherein thedeep well region of the second conductivity type which are adjacent toeach other are electrically separated from each other by a groove-shapedseparation structure which is deeper than each of the deep well regionsbut shallower than the deeper well region of the first conductivitytype.
 16. A semiconductor device according to claim 15, wherein in theshallow well region of the semiconductor device, a depletion layerformed by a junction between the low impurity concentration region andthe source region and the drain region is not in contact with the highimpurity concentration region.
 17. A semiconductor device according toclaim 15, wherein the high impurity concentration region in the shallowwell region of the semiconductor device has an impurity concentration atits peak position in a concentration range of 1×10²¹/cm³-5×10¹⁷/cm³. 18.A semiconductor device according to claim 15, wherein the low impurityconcentration region in the shallow well region of the semiconductordevice has an impurity concentration in a concentration range of1×10¹⁸/cm³-1×10¹⁶/cm³.
 19. A semiconductor device according to claim 15,wherein the semiconductor device forms a complementary circuit.
 20. Asemiconductor device according to claim 3, wherein the semiconductordevice forms a complementary circuit.
 21. A semiconductor deviceaccording to claim 14, wherein in the shallow well region of thesemiconductor device, a depletion layer formed by a junction between thelow impurity concentration region and the source region and the drainregion is not in contact with the high impurity concentration region.22. A semiconductor device according to claim 3, wherein the highimpurity concentration region in the shallow well region of thesemiconductor device has an impurity concentration at its peak positionin a concentration range of 1×10²¹/cm³-5×10¹⁷/cm³.
 23. A semiconductordevice according to claim 14, wherein the low impurity concentrationregion in the shallow well region of the semiconductor device has animpurity concentration in a concentration range of1×10¹⁸/cm³-1×10¹⁶/cm³.
 24. A semiconductor device, comprising: asemiconductor substrate of a first conductivity type; a groove-shapedseparation region provided in the semiconductor substrate; a pluralityof island-like active regions separated from one another by thegroove-shaped separation region; a deep well region of a secondconductivity type provided in at least one of the island-like activeregions, the deep well region of the second conductivity type beingsurrounded by the groove-shaped separation region; a shallow well regionof the first conductivity type provided for one of the island-likeactive regions where the deep well region surrounded by thegroove-shaped separation region exists, the shallow well region of thefirst conductivity type being surrounded by the groove-shaped separationregion; a shallow well region of the second conductivity type providedfor another one of the island-like active regions where the deep wellregion surrounded by the groove-shaped separation region does not exist,the shallow well region of the second conductivity type being surroundedby the groove-shaped separation region; a source region and a drainregion of the second conductivity type provided in the shallow wellregion of the first conductivity type; a source region and a drainregion of the first conductivity type provided in the shallow wellregion of the second conductivity type; channel regions provided betweenthe source region and the drain region of the first conductivity typeand between the source region and the drain region of the secondconductivity type; a gate insulation film provided on each of thechannel regions; and a gate electrode provided on the gate insulationfilm, wherein: each gate electrode is electrically connected to theshallow well region corresponding to the gate electrode; and the shallowwell region of the first conductivity type, the shallow well region ofthe second conductivity type, and the deep well region of the secondconductivity type are electrically separated respectively from anadjacent shallow well region of the first conductivity type, an adjacentshallow well region of the second conductivity type, and an adjacentdeep well region of the second conductivity type.
 25. A semiconductordevice according to claim 24, wherein the semiconductor substrate andthe deep well region of the semiconductor device are set to a constantvoltage.
 26. A semiconductor device according to claim 25, wherein theshallow well region of the semiconductor device has a structure in whicha high impurity concentration region is sandwiched between low impurityconcentration regions.
 27. A semiconductor device according to claim 26,wherein in the shallow well region of the semiconductor device, adepletion layer formed by a junction between the low impurityconcentration region and the source region and the drain region is notin contact with the high impurity concentration region.
 28. Asemiconductor device according to claim 26, wherein the high impurityconcentration region in the shallow well region of the semiconductordevice has an impurity concentration at its peak position in aconcentration range of 1×10²¹/cm³-5×10¹⁷/cm³.
 29. A semiconductor deviceaccording to claim 26, wherein the low impurity concentration region inthe shallow well region of the semiconductor device has an impurityconcentration in a concentration range of 1×10¹⁸/cm³-1×10¹⁶/cm³.
 30. Asemiconductor device according to claim 24, wherein the shallow wellregion of the semiconductor device has a structure in which a highimpurity concentration region is sandwiched between low impurityconcentration regions.
 31. A semiconductor device according to claim 30,wherein in the shallow well region of the semiconductor device, adepletion layer formed by a junction between the low impurityconcentration region and the source region and the drain region is notin contact with the high impurity concentration region.
 32. Asemiconductor device according to claim 30, wherein the high impurityconcentration region in the shallow well region of the semiconductordevice has an impurity concentration at its peak position in aconcentration range of 1×10²¹/cm³-5×10¹⁷/cm³.
 33. A semiconductor deviceaccording to claim 30, wherein the low impurity concentration region inthe shallow well region of the semiconductor device has an impurityconcentration in a concentration range of 1×10¹⁸/cm³-1×10¹⁶/cm³.
 34. Asemiconductor device, comprising: a semiconductor substrate; a deeperwell region of a first conductivity type provided in the semiconductorsubstrate; a groove-shaped separation region provided in the deeper wellregion; a plurality of island-like active regions separated from oneanother by the groove-shaped separation region; a deep well region of asecond conductivity type provided in at least one of the island-likeactive regions, the deep well region of the second conductivity typebeing surrounded by the groove-shaped separation region; a shallow wellregion of the first conductivity type provided for one of theisland-like active regions where the deep well region surrounded by thegroove-shaped separation region exists, the shallow well region of thefirst conductivity type being surrounded by the groove-shaped separationregion; a shallow well region of the second conductivity type providedfor another one of the island-like active regions where the deep wellregion surrounded by the groove-shaped separation region does not exist,the shallow well region of the second conductivity type being surroundedby the groove-shaped separation region; a source region and a drainregion of the second conductivity type provided in the shallow wellregion of the first conductivity type; a source region and a drainregion of the first conductivity type provided in the shallow wellregion of the second conductivity type; channel regions provided betweenthe source region and the drain region of the first conductivity typeand between the source region and the drain region of the secondconductivity type; a gate insulation film provided on each of thechannel regions; and a gate electrode provided on the gate insulationfilm, wherein: each gate electrode is electrically connected to theshallow well region corresponding to the gate electrode; and the shallowwell region of the first conductivity type, the shallow well region ofthe second conductivity type, and the deep well region of the secondconductivity type are electrically separated respectively from anadjacent shallow well region of the first conductivity type, an adjacentshallow well region of the second conductivity type, and an adjacentdeep well region of the second conductivity type.
 35. A semiconductordevice according to claim 34, wherein the semiconductor substrate, thedeep well region and the deeper well region of the semiconductor deviceare set to a constant voltage.
 36. A semiconductor device according toclaim 34, wherein the shallow well region of the semiconductor devicehas a structure in which a high impurity concentration region issandwiched between low impurity concentration regions.
 37. Asemiconductor device, comprising a semiconductor substrate of a firstconductivity type; a groove-shaped separation region provided in thesemiconductor substrate; a plurality of island-like active regionsseparated from one another by the groove-shaped separation region; adeep well region of the first conductivity type provided in at least oneof the island-like active regions, the deep well region of the firstconductivity type being surrounded by the groove-shaped separationregion; a deep well region of a second conductivity type provided foranother one of the island-like active regions where the deep well regionof the first conductivity type does not exist, the shallow well regionof the second conductivity type being surrounded by the groove-shapedseparation region; a shallow well region of the second conductivity typeprovided in an upper portion of the deep well region of the firstconductivity type, the shallow well region of the second conductivitytype being surrounded by the groove-shaped separation region; a shallowwell region of the first conductivity type provided in an upper portionof the deep well region of the second conductivity type, the shallowwell region of the first conductivity type being surrounded by thegroove-shaped separation region; a source region and a drain region ofthe second conductivity type provided in the shallow well region of thefirst conductivity type; a source region and a drain region of the firstconductivity type provided in the shallow well region of the secondconductivity type; channel regions provided between the source regionand the drain region of the first conductivity type and between thesource region and the drain region of the second conductivity type; agate insulation film provided on each of the channel regions; and a gateelectrode provided on the gate insulation film, wherein: each gateelectrode is electrically connected to the shallow well regioncorresponding to the gate electrode; and the shallow well region of thefirst conductivity type, the shallow well region of the secondconductivity type, the deep well region of the first conductivity type,and the deep well region of the second conductivity type areelectrically separated respectively from an adjacent shallow well regionof the first conductivity type, an adjacent shallow well region of thesecond conductivity type, an adjacent deep well region of the firstconductivity type, and an adjacent deep well region of the secondconductivity type.
 38. A semiconductor device according to claim 37,wherein the semiconductor substrate and the deep well region of thesemiconductor device are set to a constant voltage.
 39. A semiconductordevice according to claim 37, wherein the shallow well region of thesemiconductor device has a structure in which a high impurityconcentration region is sandwiched between low impurity concentrationregions.